The invention relates to combining coding and modulation that are used to handle a digital signal for high-frequency transmission in a noisy channel.
In an attempt to increase the communication speed of digital radio systems, binary signals have been replaced by multiple-valued signals in connection with a high-level modulation scheme. Here we consider 16-QAM ( 16-level Quadrature Amplitude Modulation) as an example of high-level modulation. Multiple-valued signals require the signal encoder and decoder to have special properties. FIG. 1 illustrates a multi-level encoding and decoding arrangement known from the document xe2x80x9cH. Imai, S. Hirakawa: A New Multilevel Coding Method Using Error-Correcting Codes, IEEE Transactions on Information Theory, Vol. IT-23, No. 3, 1977xe2x80x9d, which is incorporated herein by reference. Encoder 100 consists of a serial/parallel conversion circuit 101, M parallel binary encoders 102-105, where M is a positive integer (here M=4), and a mapping circuit 106. The output signal of the encoder 100 travels through a channel 107 and reaches a decoder 108 including a demultiplexing decoding circuit 109, which produces M parallel signal estimates, and a selection circuit 110, which reconstructs the original information from the estimates at its input. Modulation and demodulation are included in the channel part 107 of FIG. 1.
The serial/parallel conversion circuit 101 converts a stream of binary symbols into M component streams which may have different rates. Each component stream is fed into its own binary encoder 102-105. The generic definition of a multi-level encoder sets very few specific requirements to the parallel binary encoders 102-105, although in many cases they are selected to produce a coded data stream of equal rate. The mapping circuit 106 reads bits from the output of each binary encoder and maps these bits into a corresponding multi-level signal, which has one of the 2M allowed levels or states. Especially in the case of 2M-order QAM modulation M must be even and the output states of the mapping circuit 106 correspond to the allowed phase and amplitude value combinations of an oscillating signal.
FIG. 3 illustrates a so-called multi-stage decoder 300 that can be used as the decoder 108 in the arrangement of FIG. 1. At each sampling moment the input signal in line 301 is supposed to be in one of the 2M allowed states. The first metric block 302 produces a metric or a probability value that indicates, whether the least significant bit describing the state of the input signal should be 0 or 1. A decision of the corresponding decoded bit value is made in the first decoder 306. At each further horizontal level of the multi-stage decoder one of the decoders 307-309 makes a further decision, and each of the encoders 310-312 provides the respective decision in re-encoded form as an additional input to the metric block 303-305 of the remaining levels. Delay elements 314-319 take care of the mutual timing of the signal parts before and after decoding, so that after the last decision about the decoded bit value is made in block 309, multiplexer 320 may construct the original bit stream from the outputs of delay elements 317-319 and decoder 309 in a way that is reciprocal to the operation of the serial/parallel conversion circuit 101 in the transmitter (see FIG. 1).
If the computational capacity of the receiving device is high enough with respect to the rate of the incoming received signal, a feedback connection could be arranged from decoder 309 to the first metric block 302 through an additional encoder. The resulting device would be capable of so-called iterative decoding, where the first round of decisions in the decoder blocks 306 to 309 serves as an input to a second (iterative) round and so on. The more iterations on each symbol, the smaller the chance of an erroneous decoding decision.
The problem of a conventional MLC-MSD arrangement (Multi-Level Coding-Multi-Stage Decoding) is its inflexibility with respect to varying rates of coding. A radio channel is prone to fluctuating noise and interference, so different coding rates are required at different times. If the radio capacity (in terms of frequency and time) allocated to a certain radio connection is fixed and interference conditions suddenly get worse, it may be necessary to increase the amount of coding and decrease the effective data rate correspondingly to get even some data through to the receiving station. Similarly if the interference eases off, the transmitting device may use the chance to reduce coding, thereby increasing the effective data rate. This approach is naturally applicable to non-real time connections (so-called non-transparent data services) only, where a fixed data rate is not required. However, the radio system may allow the radio capacity allocations of separate connections to vary, whereby a real-time connection (transparent data services) can sustain its fixed data rate at all times and simultaneously fight interference with a variable coding rate together with a variable amount of reserved radio capacity. In any case it may be necessary to have a maximum coding rate close to 1 (exactly 1 means that no redundancy is added by coding) and a minimum coding rate as low as 0.1 (meaning that ten coded bits are transmitted per each data bit), and the possibility of choosing more or less freely therebetween according to need.
A conventional approach to enable a selection of coding rates is known from the publication xe2x80x9cEDGE Feasibility Studies, Work Item 184: Improved Data Rates through Optimised Modulation; ETSI STC SMG 2, Munich, Germany, May 12-16, 1997xe2x80x9d, which is incorporated herein by reference. This approach for transparent data services is illustrated in FIG. 4b,where data bits are input into block 401 and coded symbols are output from block 410. Blocks 401 to 405 form a so-called concatenated encoder, where block 401 first maps the data bits into preliminary symbols, block 402 performs RS (Reed-Solomon) encoding on those, block 403 interleaves the RS-coded preliminary symbols within a selectable interleaving length N1 and block 404 maps the result again into bits. A fixed-rate convolutional encoder 405 with codingrate ⅓ adds redundancy to the bit stream. The serial to parallel converter 406 sends groups of four consecutive bits in parallel into puncturing blocks 407a and 407b and after that an additional interleaver 408 performs bit interleaving over an interleaving period of four frames. Further serial to parallel converters 409a and 409b are used to feed the four manipulated parallel bit streams into a Q-O-QAM mapper 410 which operates according to a so-called Gray mapping to produce the output symbols. FIG. 4b illustrates a corresponding approach for non-transparent data services, where the RS encoder 402 has been replaced with a simple CRC (Cyclic Redundancy Check) encoder 402xe2x80x2 which adds to the bit stream a CRC checksum at predetermined intervals called frames. The purpose of a CRC checksum in each frame is not to correct errors in received frames but to detect them so that the receiving device may ask for a retransmission of a defective frame. Because the CRC calculation takes place on bit level, the conversion blocks 401 and 404 of FIG. 4a may be omitted and the interleaver block 403xe2x80x2 operates on bits and not preliminary symbols like block 403 in FIG. 4a. 
One of the drawbacks of the prior art arrangements of FIGS. 4a and 4b is that iterative decoding and Multi-Stage Decoding cannot be used as the decoding method, which impairs the performance of the system in comparison with the theoretical optimum. Another drawback is that to meet the ETSI standards (European Telecommunications Standards Institute) for real-time (transparent) data services, the concatenated codes used in blocks 402 and 405 must be rather complicated. Additionally to implement both transparent and non-transparent data services at least two alternative outer encoders are needed (blocks 402 and 402xe2x80x2) in the transmitter with the corresponding alternative decoders in the receiver, which makes the structures rather complex.
It is the object of this invention to provide a method and apparatus for encoding, modulating, demodulating and decoding in a radio system employing multiple-valued signals in transmission. It is a further object of the invention to keep the required hardware simple despite of variable coding rates and data services.
The objects of the invention are fulfilled by using multi-level coding and multi-stage decoding with hybrid concatenated codes as the component codes in the encoder.
The method according to the invention is characterised in that it comprises the steps of
a) encoding digital information in a Hybrid Concatenated Code encoder,
b) mapping the encoded digital information into multiple-valued symbols in a Multi-Level Coding encoder,
c) transmitting the multiple-valued symbols,
d) receiving the multiple-valued symbols, and
e) decoding the received multiple-valued symbols in a Multi-Stage Decoder.
The invention also applies to a transmitting device which is characterised in that it comprises
a Hybrid Concatenated Code encoder for encoding the digital information to be transmitted and
a Multi-Level Coder for mapping the encoded digital information into multiple-valued symbols,
and to a cellular radio system which is characterised in that it comprises at least one such transmitting device.
According to the invention, a Hybrid Concatenated Code encoder (HCC encoder) is used together with a Multi-Level Coding scheme (MLC scheme). Each component code of the Multi-Level Encoder consists of an HCC part, which is common to all component codes and can be implemented in a single HCC encoder before dividing the stream of data bits into variable rate component streams, and a puncturing part which is implemented separately to each component stream and which reduces the bit rate of each component stream to a common bit rate. The parallel punctured component streams can then be used as inputs to the symbol mapper using set partition mapping in the MLC scheme. Multi-Stage Decoding (MSD) can be used in the receiver to decode the received signal.
An HCC encoder consists of at least two parallel coding paths and a multiplexer (or a switch) that selects only one coding path at a time for use. One of the coding paths includes at least two concatenated simple encoders which are called the inner encoder and the outer encoder: both the inner and outer encoders are most advantageously systematic convolutional encoders with a relatively low number of states. Their operation is most advantageously complemented with a puncturing block and some interleaving. Another coding path includes only one encoder and possibly an interleaver. Together with the puncturing blocks (that reduce the data rate of the component streams after the serial to parallel conversion in the MLC encoder) the HCC encoder implements a so-called Rate Compatible Punctured Code system, where the HCC encoder implements a xe2x80x9cmotherxe2x80x9d code and the puncturing blocks take care of the adaptation of the overall coding rate to a required level.
In the receiver according to the invention, a Multi-Stage Decoder (MSD) performs demodulation and decoding from symbols into coded data bits, which are directed into a structure that is a counterpart to the HCC encoder: a demultiplexer connects the stream of coded data bits either to a one-stage decoder (if the simpler coding path was used in the HCC) or to a two-stage decoder. Iterative decoding calculations are possible both in the MSD and the latter decoder if the requirements for decoding delay are loose enough and if the receiver has the required computational capacity.